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The-four-locks-Verilog-based-design
- 基于Verilog的四位密码锁设计，采用有限状态机进行编写-The four locks Verilog-based design, finite state machine for the preparation
Verilog
- Verilog初学者使用，各种verilog的典型电路设计。包括状态机、CRC校验等。-Verilog beginners, abundant examples
verilogiic1121
- 用verilog状态机写的IIC通信模块，包括两个子模块和一个顶层模块，均为verilog源码-Written in verilog state machine IIC communication module, including two modules and a top-level module, they are all the verilog code.
Verilog-HDL-washer
- 智能洗衣机控制器 基于verilog hdl状态机 具有多种功能切换-Intelligent washing machine controller verilog hdl-based state machine has multi-functional switch
Verilog-example3
- verilog实例分析第三部分，通过实例分析讲解有限状态机的设计过程。-The third case study verilog part, by an example to explain the finite state machine design process.
32-bit-division-design-In-Verilog
- 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
class09_A
- Verilog 状态机编写按键消抖，并且testbench-Verilog write key debounce
pro
- S10420背照式CCD verilog 状态机驱动代码-S10420 back-illuminated CCD verilog state machine driver code
4LED
- 4LED流水灯程序，可更换频率，采用状态机，低电平有效亮灯，高电平熄灭(4LED water lamp program, you can change the frequency. Using state machine, low level active light, high level extinction)
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
fsm
- 有限状态机fsm 二段式编写 verilog(Finite state machine, FSM, two sections, verilog)
sdram_ip
- 完成SDRAM的上电配置，状态机编写其读写模块，存储模块，并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
lowpower
- 最大公约数（GCD）stein算法实现，低功耗状态机实现(The greatest common divisor (GCD) stein algorithm, low power state machine implementation)
信号分析与处理——MATLAB语.part1
- ① Verilog的抽象级别 ② Verilog的模块化设计 ③ 如何给端口选择正确的数据类型 ④ Verilog语言中latch的产生 ⑤ 组合逻辑反馈环 ⑥ 阻塞赋值与非阻塞赋值的不同 ⑦ FPGA的灵魂状态机 ⑧ 代码风格的重要性((1) the abstract level of Verilog The modular design of Verilog How to select the correct data type for the
xujiance
- 设计一个序检测电路，功能是检测出串行输入数据Data中的4位二进制序列1101（自左至右输入），当检测到该序列时，输出Out为1；没有检测到该序列时，输出输出Out为0，要求： （1）用状态机方法设计； （2）用Verilog HDL语言设计，用Modelsim软件做功能仿真。(A sequence detection circuit is designed to detect the 4 bit binary sequence 1101 in the serial input data D
14_ethernet_test
- 千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
Desktop
- 用Verilog编程语言来实现一个具有奇校验功能的串行发送电路，可以采用移位寄存器和有限状态机的方式来实现。(Serial transmission circuit with odd check function)
eda
- 在Verilog HDL中使用任务（task）， 利用有限状态机进行时序逻辑的设计，利用SRAM设计一个LIFO(In Verilog HDL, the task (task) is used, the finite state machine is used to design the time series logic, and a LIFO is designed by SRAM)
lession_10 led_diver
- 流水灯驱动 状态机写的 很好 已经运用有实际编程中(LED drive The state machine is well written and has been used in practical programming)
uart
- 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)